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<p>This typedef contains configuration information for the DisplayPort core.  
 <a href="struct_x_dp___config.html#details">More...</a></p>
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Data Fields</h2></td></tr>
<tr class="memitem:a1a2be6837a807d11e38d7e18eb73acc0"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#a1a2be6837a807d11e38d7e18eb73acc0">DeviceId</a></td></tr>
<tr class="memdesc:a1a2be6837a807d11e38d7e18eb73acc0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device instance ID.  <a href="#a1a2be6837a807d11e38d7e18eb73acc0">More...</a><br/></td></tr>
<tr class="separator:a1a2be6837a807d11e38d7e18eb73acc0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a26db9b137de6560d3b2690f0d4acaed0"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#a26db9b137de6560d3b2690f0d4acaed0">BaseAddr</a></td></tr>
<tr class="memdesc:a26db9b137de6560d3b2690f0d4acaed0"><td class="mdescLeft">&#160;</td><td class="mdescRight">The base address of the core instance.  <a href="#a26db9b137de6560d3b2690f0d4acaed0">More...</a><br/></td></tr>
<tr class="separator:a26db9b137de6560d3b2690f0d4acaed0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9a0799787a21f54ae0eddb8de0b7cf14"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#a9a0799787a21f54ae0eddb8de0b7cf14">SAxiClkHz</a></td></tr>
<tr class="memdesc:a9a0799787a21f54ae0eddb8de0b7cf14"><td class="mdescLeft">&#160;</td><td class="mdescRight">The clock frequency of the core instance's S_AXI_ACLK port.  <a href="#a9a0799787a21f54ae0eddb8de0b7cf14">More...</a><br/></td></tr>
<tr class="separator:a9a0799787a21f54ae0eddb8de0b7cf14"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab2987e7be375659d959a7e97a96f035a"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#ab2987e7be375659d959a7e97a96f035a">MaxLaneCount</a></td></tr>
<tr class="memdesc:ab2987e7be375659d959a7e97a96f035a"><td class="mdescLeft">&#160;</td><td class="mdescRight">The maximum lane count supported by this core instance.  <a href="#ab2987e7be375659d959a7e97a96f035a">More...</a><br/></td></tr>
<tr class="separator:ab2987e7be375659d959a7e97a96f035a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a365f2d8d2631612e1946901662a64b0b"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#a365f2d8d2631612e1946901662a64b0b">MaxLinkRate</a></td></tr>
<tr class="memdesc:a365f2d8d2631612e1946901662a64b0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">The maximum link rate supported by this core instance.  <a href="#a365f2d8d2631612e1946901662a64b0b">More...</a><br/></td></tr>
<tr class="separator:a365f2d8d2631612e1946901662a64b0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1848e773ea65e28aa85440c72c4bc9bd"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#a1848e773ea65e28aa85440c72c4bc9bd">MaxBitsPerColor</a></td></tr>
<tr class="memdesc:a1848e773ea65e28aa85440c72c4bc9bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">The maximum bits/color supported by this core instance.  <a href="#a1848e773ea65e28aa85440c72c4bc9bd">More...</a><br/></td></tr>
<tr class="separator:a1848e773ea65e28aa85440c72c4bc9bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac84b8057614ed03b57a81093dba7db53"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#ac84b8057614ed03b57a81093dba7db53">OctaPixelEn</a></td></tr>
<tr class="memdesc:ac84b8057614ed03b57a81093dba7db53"><td class="mdescLeft">&#160;</td><td class="mdescRight">Octa pixel support by this core instance.  <a href="#ac84b8057614ed03b57a81093dba7db53">More...</a><br/></td></tr>
<tr class="separator:ac84b8057614ed03b57a81093dba7db53"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3f284f0e071c5a742ac50c143ea66a47"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#a3f284f0e071c5a742ac50c143ea66a47">QuadPixelEn</a></td></tr>
<tr class="memdesc:a3f284f0e071c5a742ac50c143ea66a47"><td class="mdescLeft">&#160;</td><td class="mdescRight">Quad pixel support by this core instance.  <a href="#a3f284f0e071c5a742ac50c143ea66a47">More...</a><br/></td></tr>
<tr class="separator:a3f284f0e071c5a742ac50c143ea66a47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8bd1f6452601ab45a534e5e567cef1e6"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#a8bd1f6452601ab45a534e5e567cef1e6">DualPixelEn</a></td></tr>
<tr class="memdesc:a8bd1f6452601ab45a534e5e567cef1e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Dual pixel support by this core instance.  <a href="#a8bd1f6452601ab45a534e5e567cef1e6">More...</a><br/></td></tr>
<tr class="separator:a8bd1f6452601ab45a534e5e567cef1e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a804bd984a9fe7f1e19d780bf57ed17a7"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#a804bd984a9fe7f1e19d780bf57ed17a7">YCrCbEn</a></td></tr>
<tr class="memdesc:a804bd984a9fe7f1e19d780bf57ed17a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">YCrCb format support by this core instance.  <a href="#a804bd984a9fe7f1e19d780bf57ed17a7">More...</a><br/></td></tr>
<tr class="separator:a804bd984a9fe7f1e19d780bf57ed17a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9b41ca69bf5e0ae7300c9a5abd5b34fe"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#a9b41ca69bf5e0ae7300c9a5abd5b34fe">YOnlyEn</a></td></tr>
<tr class="memdesc:a9b41ca69bf5e0ae7300c9a5abd5b34fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">YOnly format support by this core instance.  <a href="#a9b41ca69bf5e0ae7300c9a5abd5b34fe">More...</a><br/></td></tr>
<tr class="separator:a9b41ca69bf5e0ae7300c9a5abd5b34fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad55c96c3cb3b68375ef00270f99624c4"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#ad55c96c3cb3b68375ef00270f99624c4">PayloadDataWidth</a></td></tr>
<tr class="memdesc:ad55c96c3cb3b68375ef00270f99624c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">The payload data width used by this core instance.  <a href="#ad55c96c3cb3b68375ef00270f99624c4">More...</a><br/></td></tr>
<tr class="separator:ad55c96c3cb3b68375ef00270f99624c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b28d245a94a32d3cf47f2a48044ed3d"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#a2b28d245a94a32d3cf47f2a48044ed3d">SecondaryChEn</a></td></tr>
<tr class="memdesc:a2b28d245a94a32d3cf47f2a48044ed3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This core instance supports audio packets being sent by the secondary channel.  <a href="#a2b28d245a94a32d3cf47f2a48044ed3d">More...</a><br/></td></tr>
<tr class="separator:a2b28d245a94a32d3cf47f2a48044ed3d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aca6d4ff74a97c61024cb9d01208beb15"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#aca6d4ff74a97c61024cb9d01208beb15">NumAudioChs</a></td></tr>
<tr class="memdesc:aca6d4ff74a97c61024cb9d01208beb15"><td class="mdescLeft">&#160;</td><td class="mdescRight">The number of audio channels supported by this core instance.  <a href="#aca6d4ff74a97c61024cb9d01208beb15">More...</a><br/></td></tr>
<tr class="separator:aca6d4ff74a97c61024cb9d01208beb15"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad2199240482b0fe872899ab24eb65cab"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#ad2199240482b0fe872899ab24eb65cab">MstSupport</a></td></tr>
<tr class="memdesc:ad2199240482b0fe872899ab24eb65cab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multi-stream transport (MST) mode is enabled by this core instance.  <a href="#ad2199240482b0fe872899ab24eb65cab">More...</a><br/></td></tr>
<tr class="separator:ad2199240482b0fe872899ab24eb65cab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a19f28705ad36d2977c7000949184fb9c"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#a19f28705ad36d2977c7000949184fb9c">NumMstStreams</a></td></tr>
<tr class="memdesc:a19f28705ad36d2977c7000949184fb9c"><td class="mdescLeft">&#160;</td><td class="mdescRight">The total number of MST streams supported by this core instance.  <a href="#a19f28705ad36d2977c7000949184fb9c">More...</a><br/></td></tr>
<tr class="separator:a19f28705ad36d2977c7000949184fb9c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1632df176c6aa05831f6456bc8c0ea6e"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#a1632df176c6aa05831f6456bc8c0ea6e">DpProtocol</a></td></tr>
<tr class="memdesc:a1632df176c6aa05831f6456bc8c0ea6e"><td class="mdescLeft">&#160;</td><td class="mdescRight">The DisplayPort protocol version that this core instance is configured for.  <a href="#a1632df176c6aa05831f6456bc8c0ea6e">More...</a><br/></td></tr>
<tr class="separator:a1632df176c6aa05831f6456bc8c0ea6e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a69d4f2f8c4557a548f9a0d32fe39ef18"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp___config.html#a69d4f2f8c4557a548f9a0d32fe39ef18">IsRx</a></td></tr>
<tr class="memdesc:a69d4f2f8c4557a548f9a0d32fe39ef18"><td class="mdescLeft">&#160;</td><td class="mdescRight">The type of DisplayPort core.  <a href="#a69d4f2f8c4557a548f9a0d32fe39ef18">More...</a><br/></td></tr>
<tr class="separator:a69d4f2f8c4557a548f9a0d32fe39ef18"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>This typedef contains configuration information for the DisplayPort core. </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="a26db9b137de6560d3b2690f0d4acaed0"></a>
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          <td class="memname">UINTPTR XDp_Config::BaseAddr</td>
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<p>The base address of the core instance. </p>

<p>Referenced by <a class="el" href="group__dp.html#ga99e89fe4b5550c32cef410fffab99318">XDp_CfgInitialize()</a>.</p>

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          <td class="memname">u16 XDp_Config::DeviceId</td>
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<p>Device instance ID. </p>

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<a class="anchor" id="a1632df176c6aa05831f6456bc8c0ea6e"></a>
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          <td class="memname">u8 XDp_Config::DpProtocol</td>
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<p>The DisplayPort protocol version that this core instance is configured for. </p>
<p>0 = v1.1a, 1 = v1.2, 2 = v1.4. </p>

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<a class="anchor" id="a8bd1f6452601ab45a534e5e567cef1e6"></a>
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          <td class="memname">u8 XDp_Config::DualPixelEn</td>
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<p>Dual pixel support by this core instance. </p>

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          <td class="memname">u8 XDp_Config::IsRx</td>
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<p>The type of DisplayPort core. </p>
<p>0 = TX, 1 = RX. </p>

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          <td class="memname">u8 XDp_Config::MaxBitsPerColor</td>
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<p>The maximum bits/color supported by this core instance. </p>

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          <td class="memname">u8 XDp_Config::MaxLaneCount</td>
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<p>The maximum lane count supported by this core instance. </p>

<p>Referenced by <a class="el" href="group__dp.html#gaa1d4f025616d218cff6dc47ca3456ff4">XDp_IsLaneCountValid()</a>.</p>

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<p>The maximum link rate supported by this core instance. </p>

<p>Referenced by <a class="el" href="group__dp.html#ga99e89fe4b5550c32cef410fffab99318">XDp_CfgInitialize()</a>.</p>

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<p>Multi-stream transport (MST) mode is enabled by this core instance. </p>

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<p>The number of audio channels supported by this core instance. </p>

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<p>The total number of MST streams supported by this core instance. </p>

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          <td class="memname">u8 XDp_Config::OctaPixelEn</td>
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<p>Octa pixel support by this core instance. </p>

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<p>The payload data width used by this core instance. </p>

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<p>Quad pixel support by this core instance. </p>

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          <td class="memname">u32 XDp_Config::SAxiClkHz</td>
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<p>The clock frequency of the core instance's S_AXI_ACLK port. </p>

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          <td class="memname">u8 XDp_Config::SecondaryChEn</td>
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<p>This core instance supports audio packets being sent by the secondary channel. </p>

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          <td class="memname">u8 XDp_Config::YCrCbEn</td>
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<p>YCrCb format support by this core instance. </p>

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          <td class="memname">u8 XDp_Config::YOnlyEn</td>
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<p>YOnly format support by this core instance. </p>

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